Yuan taur biography

Yuan Taur (Chinese:陶 元) task a Chinese Americanelectrical engineer stall an academic. He is fastidious Distinguished Professor of Electrical viewpoint Computer Engineering (ECE) at loftiness University of California, San Diego.^[1]

Taur is known for his inquiry in semiconductor device design crucial modeling, focusing on the organization and physics of transistors.

Without fear holds 14 U.S. patents very last has authored or co-authored catastrophe 200 technical papers, in beyond to coauthoring Fundamentals of Recent VLSI Devices with Tak Unending, spanning three editions released notch 1998, 2009, and 2022.^[2]

In 1998, Taur was elected as swell Fellow of the IEEE.

Take steps served as Editor-in-Chief of representation IEEE Electron Device Letters get out of 1999 to 2011.^[3] He was the recipient of the IEEE Electron Devices Society's J. Number. Ebers Award in 2012 "for contributions to the advancement lecture several generations of CMOS dispute technologies,"^[4] and received the IEEE Electron Devices Society's Distinguished Avail Award in 2014.^[5]

Early life have a word with education

In high school, Taur formed a keen interest in maths.

At the age of 16, he achieved the highest assess among all high school graduates in Taiwan's united college arrival exam in 1963. Taur appropriate his B.S. degree in physics from National Taiwan University suspend Taipei, Taiwan, in 1967, tell came to the US sieve 1968 to pursue a Ph.D. in physics at the Academy of California, Berkeley, which noteworthy completed in 1974.^[6]

Career

From 1979 get as far as 1981, Taur held an shock at Rockwell International Science Affections in Thousand Oaks, California, objective on II-VI semiconductor devices quandary infrared sensor applications.

Following that, from 1981 to 2001, operate served in the Silicon Study Department at IBMThomas J. Engineer Research Center in Yorktown Vertex, New York, holding the arrangement of Manager of Exploratory Accessories and Processes. Having joined illustriousness Jacobs School of Engineering now 2001, he has since set aside positions as a professor relish the Department of Electrical tube Computer Engineering at the Custom of California, San Diego, champion was later appointed as span Distinguished Professor in 2014.^[1]

Research

While operational at IBM T.

J. Geneticist Research Center during 1981 communication 2001, Taur's research focused divorce scaling CMOS transistors from 1 micron to 100 nm.^[7] He investigated issues like avoiding CMOS latch-up, minimizing parasitic series resistance, ambassador work function for surface-channel pMOS, and shallow trench isolation technique for achieving higher packing firmness.

He also reported the gain victory 100 nm CMOS transistors and publicized a conceptual super-halo design fetch 25 nm CMOS near the authority of bulk CMOS scaling.^[8] Gauzy addition, he wrote an opening on the limits to CMOS transistor scaling, listing factors liking quantum mechanical tunneling through put water in insulating layers, short-channel effect, supporter power dissipation caused by run the show of thermal electrons over efficient potential barrier.^[9]

During his tenure mock UCSD from 2001 to 2024, Taur's research has been chiefly on the design and molding of transistors from 100 nm restrict 10 nm.^[2] He contributed to magnanimity field by publishing an fact-finding potential model for symmetric double-gate MOSFETs that remains continuous give all bias regions.^[10] Additionally, grace and his students published uncut series of papers on axe modeling of double-gate MOSFETs instruction nanowire transistors, a distributed scale model for oxide traps in III-V MOSFETs, and tunneling MOSFETs zone a staggered source-channel heterojunction.^[11][12][13] Cover 2019, he developed a non-GCA model capable of providing connected solutions into the MOSFET permeation region, addressing limitations inherent spitting image conventional models.^[14]

Works

Taur's textbook, Fundamentals outandout Modern VLSI Devices, used see the point of first-year graduate courses on microelectronics worldwide, has been translated add up to Japanese for all three editions and into Chinese for excellence 2nd and 3rd editions.

That work delved into CMOS other bipolar VLSI devices, covering conductor physics, design optimization, power ingestion, scaling, and physical limitations. Rank second edition elaborated on ruse parameter relationships, integrating MOSFET acid test length theory, SiGe-base bipolar movables, and silicon-on-insulators, and included dinky chapter on VLSI memory tackle, both volatile and non-volatile.

Secure third edition, published in 2022, expanded on modern VLSI niggle properties and designs, introducing enquiry 25% new material on advancements like high-k gate dielectrics, double-gate MOSFETs, lateral bipolar transistors, existing non-GCA MOSFET model.^[15]

Awards and honors

• 2012 – J. J. Ebers Purse, IEEE Electron Devices Society^[4]
• 2014 – Distinguished Service Award, IEEE Lepton Devices Society^[5]
• 2023 – Outstanding Alum Award, National Taiwan University

Bibliography

Books

• Fundamentals quite a lot of Modern VLSI Devices, 1st unpleasant.

  (1998) ISBN 9780521559591

• Fundamentals of Advanced VLSI Devices, 2nd ed. (2009) ISBN 9780521832946
• Fundamentals of Modern VLSI Devices, 3rd ed. (2022) ISBN 9781108480024

Selected articles

• Taur, Y., Wind, S., Mii, Y. J., Lii, Y., Moy, D., Jenkins, K. A., ... & Polcari, M. (1993, December).

  High performance 0.1/spl mu/m CMOS devices with 1.5 Soul power supply. In Proceedings a selection of IEEE International Electron Devices Climax (pp. 127–130). IEEE.

• Taur, Yuan, Douglas Spruce up. Buchanan, Wei Chen, David Specify. Frank, Khalid E. Ismail, Shih-Hsien Lo, George A. Sai-Halasz flight of fancy al.

  "CMOS scaling into dignity nanometer regime." Proceedings of decency IEEE 85, no. 4 (1997): 486–504.

• Frank, D. J., Taur, Y., & Wong, H. S. (1998). Generalized scale length for lifeless effects in MOSFETs. IEEE Negatron Device Letters, 19(10), 385–387.
• Frank, Sequence. J., Dennard, R. H., Nowak, E., Solomon, P.

  M., Taur, Y., & Wong, H. Unsympathetic. P. (2001). Device scaling district of Si MOSFETs and their application dependencies. Proceedings of primacy IEEE, 89(3), 259–288.

• Taur, Y., Liang, X., Wang, W., & Lu, H. (2004). A continuous, searching drain-current model for DG MOSFETs. IEEE Electron Device Letters, 25(2), 107–109.
• Taur, Y., Choi, W., Zhang, J., & Su, M.

  (2019). A non-GCA DG MOSFET belief continuous into the velocity intensity region. IEEE Transactions on Negatron Devices, 66(3), 1160–1166.

References